CSIT Laboratory




Constantinescu Laurentiu
Staverescu Iulian
Vicovan Ionut

Procesor DLX

Chapter 2 - Implementation

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Table of contents :


2.1 Instructions Set of the DLX processor

Load/Store
No Instruction Description COP
1 LB load byte 6'b000000
2 LBU load unsigned byte 6'b000001
3 LH load half byte 6'b000010
4 LHU load unsigned half byte 6'b000011
5 LW load word 6'b000100
6 LF load float 6'b000101
7 LD load double float 6'b000110
8 LHI load immediate 6'b000111
9 SB store byte 6'b001000
10 SH store half byte 6'b001001
11 SW store word 6'b001010
12 SF store float 6'b001011
13 SD store double 6'b001100
UAL Instructions with immediate operand
No Instruction Descrption COP
14 ADDI add with immediate operand 6'b010000
15 SUBI sub with immediate operand 6'b010001
16 SII immediate logical and 6'b010010
17 SAUI immediate or 6'b010011
18 XSAUI immediate xor 6'b010100
19 SLLI immediate logical left shift 6'b010101
20 SRLI immediate logical shift 6'b010110
21 SRAI immediate artihmetical shift 6'b010111
22 ADDUI immediate unsigned sum 6'b011110
23 SUBUI immediate unsigned difference 6'b011111
SET Instructions with immediate operand
No Instruction Description COP
24 SLTI Set less than immediate 6'b011000
25 SGTI Set greater than immediate 6'b011001
26 SLEI Set less or equal immediate 6'b011010
27 SGEI Set greater or equal immediate 6'b011011
28 SEQI Set equal immediate 6'b011100
29 SNEI Set not equal immediate 6'b011101
Jump Instructions
No Instruction Description COP
30 JMP jump at the adress immediate 6'b100000
31 JR return at the adress rs 6'b100001
32 JAL call from adressimmediate 6'b100010
33 JALR call from adress rd 6'b100011
34 TRAP Instruction TRAP 6'b100100
35 RET return at the adress from RG[31] 6'b100101
Branch Instructions
No Instruction Description COP
36 BEQ branch if equal 6'b110000
37 BNE branch if not equal 6'b110001
Others instructions
No Instruction Description COP
38 NOP no operation 6'b111101
39 R3 Instructions that need 3 registers(extended) 6'b111110
40 HALT Instruction halt 6'b111111
Extended Instructions. The instructions R-Rare used and COP=R3
UAL Instructions
No Instruction Description func
41 ADD add 11'b00000000000
42 ADDU unsigned add 11'b00000000001
43 SUB difference 11'b00000000010
44 SUBU unsigned difference 11'b00000000100
45 MULT mulitply 11'b00000000101
46 MULTU unsigned multiply 11'b00000000110
47 DIV divide 11'b00000000111
48 DIVU unsigned divide 1'b00000001000
49 SI logical and 11'b00000001001
50 SAU logical or 11'b00000001010
51 XSAU xor 11'b00000001011
52 SLL logical left shift 11'b00000001100
53 SRL logical right shift 11'b00000001101
54 SRA arithmetical right shift 11'b00000001110
Floating Point Instructions
55 ADDF floating point add (float) 11'b00000100000
56 ADDD floating point add (double) 11'b00000100001
57 SUBF floating point sub (float) 11'b00000100010
58 SUBD floating point sub (double) 11'b00000100100
59 MULTF floating point multiply (float) 11'b00000100101
60 MULTD floating point multipliy (double) 11'b00000100110
61 DIVF floating point divide (float) 11'b00000100111
62 DIVD floating point divide (double) 11'b00000101000
Set Instructions
63 SLT set less than 11'b00000110000
64 SGT set greater than 11'b00000110001
65 SLE set less or equal than 11'b00000110010
66 SGT set greater or equal 11'b00000110011
67 SEQ set equal 11'b00000110100
68 SNE set not equal 11'b00000110101
Data transfer instructions
69 MOVS2I move from special register RAI to RG 1'b00001000001
70 MOVI2S move from RG to special register RAI 11'b00001000000
71 MOV move from RG to RG 11'b00001000010
72 MOVF move float 11'b00001000011
73 MOVD move double 11'b00001000100


Program example for DLX processor :

000111_00 000_00011 11111111 11110001 // 0: lhi 0 3 -15 --- rg[3]=(-15)(c)<< 16
010111_00 011_00100 00000000 00010000 // 4: srai 3 4 16 --- rg[4]=rg[3]>>16(a)=-15(c)
000100_00 100_00010 00000000 00110111 // 8: lw 4 2 55 --- rg[2]=mem[55+rg[4]]=mem[40]=127=7fh
010000_00 010_00001 00000000 00010111 //12: addi 2 1 23 --- rg[1]=rg[2]+23=150=96h
001001_00 000_00001 00000000 01000000 //16: sh 0 1 64 --- mem[64+0]=rg[1]=98h
001001_00 000_00010 00000000 01000100 //16: sh 0 2 68 --- mem[68+0]=rg[2]=7fh
111110_00 010_00001 00011_000 00000101 //20: mult 2 1 3 --- rg[3],rg[4]=rg[2]*rg[1]
001010_00 000_00011 00000000 01001000 //24: sw 0 3 72 --- mem[72+0]=rg[3]=0h
001010_00 000_00100 00000000 01001100 //28: sw 0 4 76 --- mem[76+0]=rg[4]=4a6ah
111111_00 00000000 00000000 00000000 //32: halt
00000000 00000000 00000000 01111111 //40: 127

After the program loading, memory is:

00011100_00000011_11111111_11110001
01011100_01100100_00000000_00010000
00010000_10000010_00000000_00110111
01000000_01000001_00000000_00010111
00100100_00000001_00000000_01000000
00100100_00000010_00000000_01000100
11111000_01000001_00011000_00000101
00101000_00000011_00000000_01001000
00101000_00000100_00000000_01001100
11111100_00000000_00000000_00000000
00000000_00000000_00000000_01111111

After the program running, memory will be

00011100_00000011_11111111_11110001
01011100_01100100_00000000_00010000
00010000_10000010_00000000_00110111
01000000_01000001_00000000_00010111
00100100_00000001_00000000_01000000
00100100_00000010_00000000_01000100
11111000_01000001_00011000_00000101
00101000_00000011_00000000_01001000
00101000_00000100_00000000_01001100
11111100_00000000_00000000_00000000
00000000_00000000_00000000_01111111
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
xxxxxxxx_xxxxxxxx_00000000_10010110
xxxxxxxx_xxxxxxxx_00000000_01111111
00000000_00000000_00000000_00000000
00000000_00000000_01001010_01101010
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx

2.3 Source code

Source code is too big to fit here.
If you want to see it click here. (for Netscape users click here.)
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