



Constantinescu Laurentiu
Staverescu Iulian
Vicovan Ionut

Procesor DLX

|
|
Introduction - DLX Processor
[Back to the first page]
[Next Chapter]
This projects presents the implementation in Verilog of a DLX numeric processor. The DLX processor has :
- An architecture with 32 general registers RG;
- Word length : 32 bits, with the fallowing posibilities to manipulate the information : byte
(8 bits), half-word (16 bits), word (32 bits) and double word (64 bits);
- It can operate binary with integer numbers with sign (2'complement)
and without sign and also with short and long floating point numbers (IEEE 754 Standard);
- ALU has three buses: two surse buses S1, S2 and one destination bus D;
- The general registers RG[ 32: 32] are biports and they have two output buffer registers
TS1, TS2 and one input buffer register TD. Those registers can not be accessed by the
normal user;
- RG[0] is always 0;
- It has 32 regsiters F[32:32] with 32 bits for floating point operations, that can be
used as pairs (F0, F2,…, F30) with double length operands;
- A special register is used for status information, for floating point operations:
the results of comparisons, the exceptions etc.
- The Big Endian mode is used for adressing the memory, with 32 bits length
adresses;
- The exchange of data betwen memory and RG or F is made using instructions Load/Store;
- The accesses that involve RG can be using a byte, half-word and word;
- The accesses that involve F can be in simple and double precision;
- All the intructions have 32 bits;
- They are three type of instructions : R, I, J;
- They are four categories of instructions: Load / Store / Data transfer,related to ALU
/ Jumps, Floating point.
Big Endian
The big endian adressing mode is a way of describing the sequence in which multibyte numbers are stored in a computer's memory.
The most significant byte is stored in the lowest memory address, which is the address of the data. Since TCP defines the byte ordering for network data, end-nodes must call a processor-specific convert utility (which would do nothing if the machine's native byte-ordering is the same as TCP's) that acts on the TCP and IP header information only. In a TCP/IP packet, the first transmitted data is the most significant byte.
Most UNIXes (for example, all System V) and the Internet are Big Endian. Motorola 680x0 microprocessors (and therefore Macintoshes), Hewlett-Packard PA-RISC, and Sun SuperSPARC processors are Big Endian. The Silicon Graphics MIPS and IBM/Motorola PowerPC processors are both Little and Big Endian (bi-endian).
The term is used because of an analogy with the story Gulliver's Travels, in which Jonathan Swift imagined a never-ending fight between the kingdoms of the Big-Endians and the Little-Endians, whose only difference is in where they crack open a hard-boiled egg.
[Back to the first page]
[Up]
[Next Chapter]
|