



Constantinescu Laurentiu
Staverescu Iulian
Vicovan Ionut

Procesor DLX

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Chapter 1
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Table of contents :
1.1 The hardware resources of the processor are:
- ALU (Arithmetic Logic Unit for integers);
- RG[ 32: 32] - biport general registers;
- TS1, TS2, TD - buffer registers for general registers, they can not be accessed by the programmer;
- TEMP- temporary register, that can also not be accessed by the programmer;
- RAI – The register of the interrupt adress (special register);
- CP – Program counter;
- RA, RD - The adress register and data register;
- RI – Register for the instruction;
- M – The main memory;
1.2 ALU Operations are:
- arithmetic/logical operations : S1+ S2; S1 – S2; S1 . S2; S1 . S2; S1 . S2;
- shift operations : S1 < < S2 (logical shift left); S1 > > S2 (logical shift wrigth);
- S1 > > a S2 (arithmetical shift wright);
- constants: 0; 1.
1.3 Types of instructions
All the instructions have 32 bits, 6 of them are used for coding the operation.
- Instructions of type I (immediate) have the format :
6 |
5 |
5 |
16 |
COP |
rs |
rd |
immediate |
where :
- COP is the operation code;
- rs, rd are the adress for the source and destination registers;
- immediate is the adress or the immediate operand;
The instructions that fallow this format are:
- Load/ Store byte, half-word, word;
- Immediate instructions (with immediate operand): RG[ rd] <- RG[ rs] @ immediate, where @ is a arithmetical/logical operator;
- Conditional ramification : rs – register, rd – unused;
- Jump to adress specified by the register, with or without returning:
rt= 0, rs = destination, immediate= 0.
- Instructions of type R (Register - Register)
6 |
5 |
5 |
5 |
11 |
COP |
rs |
rt |
rd |
func |
The operands are placed in the general registers specified by fields rs and rt,
and the result is placed in the register specified by field rd.
The field func is an extention of the operation code that allows us to manage
more instructions than we could using a 6 bits code.
This field is coding the arithmetical and logical instruction, the instructions
foar Loading/Storing in/from the special register RAI and the shift instructions:
RG[ rd] <- RG[ rs] (func) RG[ rt].
- Instructions of type J
6 |
26 |
COP |
immediate/26 bits offset |
The field immediate/offset is used to generate the jump adress.
The instructions that fallows this format are : simple jump, return (RET) and interrupt
(TRAP).
1.4 Adressing modes in instructions
- Immediate mode. The operand is placed in the instruction :
- The register mode. The operand is placed in a register specified by the field rs.
- With based offset.
The adress is the sum of a general register and the immediate field.
COP |
rs |
rd |
immediate/16 bits offset |
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Memory
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byte/half-word/word in memory |
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general register
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- Related to CP, with an 16 bits offset
COP |
rs |
rd |
immediate/offset pe 16 biti |
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Memory
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byte/half-word/word in memory |
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program counter
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- Related to CP, with 26 bits offset
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Memory
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byte/half-word/word in memory |
... |
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contor program
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