



Constantinescu Laurentiu
Staverescu Iulian
Vicovan Ionut

Procesor DLX

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Annex - Diagrams
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Diagrams for command unit (UC).
Table of contents :
For simplicity, the floating point instructions have not been shown here. The interrupts
as well.
1. Diagram for steps IF and RD
2. Diagram for steps EXE and WB of Load/Store and data transfer instructions.
Instructions :
- LB, LBU, LH, LHU, LW,
- SW,
- MOVI2S and MOVS2I
For Load/Store instructions the effective adresse is calculated first and then it is
placed in RA. The Store and Load instructions are treated separately.
3. Diagram for steps EXE and WB of ALU instructions.
Instructions:
- ADD, ADDI, SUB, SUBI,
- AND, ANDI, OR, ORI, XOR, XORI,
- SLL, SLLI, SRL, SRLI, SRA, SRAI,
- LHI.
The second operand, for simplicity, it has been placed in TEMP register.
Register (R-R) |
Immediate (R-I) |
4. Diagram for steps EXE and WB of SET instructions.
Instructions:
- SEQ, SNE, SLT, SGE, SGT, SLE.
After the placement in TEMP register of a register or immediate operand, the operation of comparison betwen TEMP and TS1 is executed. The result is placed in TD and then in RG[rd].
Register (R-R) |
Immediate (R-I) |
5. Diagram for steps EXE and WB of jump instructions.
Instructions:
For JAL and JAR instructions, the return adress is placed in TD, before the
placement of the new adress in CP. TD is placed in RG[31]. The TRAP instruction
save the adress in RAI. The immediate 26 bits offset has the sign extension at the
left.
6. Diagrams for steps EXE of branch instruction
The BEQ and BNE instructions verifiy TS1 (where it has been placed RG[rs]). If is
zero the branch is executed at CP + Offset(16 biti), if not at CP + 4.
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